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? 2012-2016 microchip technology inc. ds60001302b-page 1 eqco62r20.3/eqco31r20.3 features complies with the coaxpress v1.1 camera standard ( 1 ) supports up to 68 meters of cable at 6.25 gbps using high-quality coax supports up to 212 meters of cable at 1.25 gbps using high-quality coax single-chip solutions for both the camera side and the frame grabber side, making a bidirectional connection over a single 75 ? coax cable full-duplex, bidirectional data channel - downlink speeds from 1.25 gbps up to 6.25 gbps; differential interfacing straightforward with internal termination resistors - uplink supporting 21 mbps, allowing nanoseconds precise triggering events driven by the frame grabber supports power distribution over the coax up to 900 ma, powering the camera through the same coax transporting data signals low power consumption (<70 mw, 1.2v supply) 16-pin, 0.65 mm pin pitch, 4 mm qfn package small pcb footprint for eqco62r20 and off-chip components, with guaranteed rf-performance -40c to +85c industrial temperature range pb-free and rohs compliant applications high-definition/high-bandwidth links to cameras machine vision for semiconductor chips and display panel inspection systems military, aerospace, medical applications broadcast and surveillance camera systems traffic license plate and monitoring systems high-speed inspection systems for food inspection, bottling inspection, panel inspection, etc. any application requiring a single coax cable which carries power, video data and camera control stream. introduction the eqco62t/r20 ( 2 ) chipset is a driver/equalizer chipset that forms a bidirectional, full-duplex communication link over a single coax cable. the eqco62t/r20 chipset is designed to transport up to 6.25 gbps over the downlink channel and to trans- port 21 mbps over the uplink channel. the eqco62t20 is designed to transmit the downlink sig- nal at up to 6.25 gbps and receive the uplink signal. the eqco62r20 is designed to receive the downlink signal at up to 6.25 gbps and to transmit the uplink sig- nal. power can be transferred over the same cable via external inductors. the chipset is designed to work with several types of 75 ? coaxial cables, including legacy cables as well as thin, flexible lightweight cables. note 1: coaxpress v1.1 standard. free down- load from the jiia website: http://jiia.org/en/standardization/list/ 2: the eqco31t20 and eqco31r20 are lower-speed versions of the eqco62t20 and eqco62r20, with a maximum bit rate of 3.125 gbps for the high-speed downlink and the same uplink speed. eqco62r20.3 6.25 gbps asymmetric coax equalizer/ eqco31r20.3 3.125 gbps as ymmetric coax equalizer downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 2 ? 2012-2016 microchip technology inc. typical link performance table 1 , table 2 and table 3 give an overview of typical link performance at room temperature for the link containing the eqco62t20 coax driver in conjunction with the eqco62r20 receiver, using the downlink channel, uplink channel and power transmission simultaneously. performance for eqco62t/r20 and eqco31t/r20 is equal for bit rates up to 3.125 gbps. table 1: belden typical link performance name belden 7731a belden 1694a belden 1505a belden 1505f belden 1855a type long distance industry standard compromise coax flexible thinnest cable diameter (mm) 10.3 6.99 5.94 6.15 4.03 1.25 gbps (m) 194 130 107 80 55 2.5 gbps (m) 162 110 94 66 55 3.125 gbps (m) 147 100 86 60 55 5.0 gbps (m) 87 60 52 35 38 6 . 2 5 g b p s ( m )5 84 03 52 32 5 table 2: gepco typical link performance name gepco vhd1100 gepco vsd2001 gepco vpm2000 gepco vhd2000m gepco vdm230 type long distance industry standard compromise coax flexible thinnest cable diameter (mm) 10.3 6.91 6.15 6.15 4.16 1.25 gbps (m) 212 140 109 81 66 2.5 gbps (m) 185 120 94 67 66 3.125 gbps (m) 169 110 86 61 62 5.0 gbps (m) 102 66 53 36 38 6 . 2 5 g b p s ( m )6 84 43 52 42 5 table 3: canare typical link performance ( 1 ) name canare l-7cfb canare l-5cfb canare l-4cfb canare l-3cfb canare l-2.5cfb type long distance industry standard compromise coax thin cable thinnest cable diameter (mm) 10.2 7.7 6.1 5.5 4 1.25 gbps (m) 165 118 94 72 43 2.5 gbps (m) 135 98 79 66 43 3.125 gbps (m) 122 88 71 60 43 5.0 gbps (m) 71 52 42 36 30 6 . 2 5 g b p s ( m )4 63 42 82 42 0 note 1: specifications from canare are only up to 2 ghz. 5 gbps and 6.25 gbps performance are by extrapolation. downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 3 eqco62r20.3/eqco31r20.3 table of contents 1.0 device overview ....................................................... ...................................................... ............................................................. 4 2.0 application information.................................................... ................................................. ............................................................ 9 3.0 electrical characteristics .......................................................... ........................................ .......................................................... 16 4.0 packaging................................................................................. .................................................................................................. 18 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 4 ? 2012-2016 microchip technology inc. 1.0 device overview the eqco62t/r20 single-coax chipset is designed to simultaneously transmit and receive signals on a single 75 ? coax cable. in one direction, a downlink signal is transmitted. in the opposite direction, a lower-speed uplink is provided. the eqco62t/r20 chipset consists of two chips. the eqco62t20 is a high-speed line driver with an integrated low-speed receiver. the eqco62r20 is a high-speed receiver with an integrated low-speed transmitter. figure 1-1 illustrates a typical eqco62t/r20 link setup. the downlink signal is transmitted with 600 mv transmit amplitude at the eqco62t20 side. this signal is attenuated in the coax and recovered by an equalizer integrated in the eqco62r20. the low-speed uplink is transmitted with a lower amplitude of 130 mv to limit the crosstalk with the downlink channel. the downlink channel is intended for 8b/10b nrz coded data with bitrates from 1.25 gbps up to 6.25 gbps. the low-speed uplink operates at a bit rate of 21 mbps, and has a single-ended lvtll input and output. in addition to the downlink channel and the low-speed uplink, the system allows power transmission over the coax by using ferrite beads and external inductors. these external inductors give the communication channel a high-pass characteristic. the uplink receiver inside the eqco62t20 chip recovers the signal lost by this high-pass filter. appropriate inductors need to be selected for correct operation of the link. correct operation is only guaranteed with the inductor combination used in figure 2-1 , even though other components might be suited. the eqco62t/r20 chipset is compatible with the coaxpress v1.1 camera standard. figure 1-1: typical eqco62t/r20 link setup up to 212 meters 75 coax high denition camera eqco 62t20 frame store + camera control up to 6.25 gbps downlink 21 mbps uplink up to 900 ma dc up to 900 ma dc eqco62r20 21 mbps uplink up to 6.25 gbps downlink downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 5 eqco62r20.3/eqco31r20.3 1.1 pinout and pin description figure 1-2: eqco62r20.3 pin diagram(viewed from top) table 1-1: eqco62r20. 3 pin descriptions pin number pin name signal type description (tab) gnd power use as single-point ground. 13, 16 vcc power connect to 1.2v of power supply. 1, 4, 9, 12 gnd power connect to ground of power supply. 2, 3 sdip, sdin cml input serial input positive/negative differential serial input. connect sdin to shield of cable via termination network. external 15 ? resistors required. 11, 10 sdop/sdon cml output serial output positive/negative differential serial output. output has a swing of 2x600 mv and has 2x50 ? on-chip termination resistors. 5 lfi input uplink input signal. lvttl signal with 1.2v input swing. external series resistor is required for 2.5v (3.9 k ? ) or 3.3v (6.2 k ? ) input swing. 6 ampr input connected to vcc by a resistor that selects output swing of the uplink signal. typical value is r amp = 1.2 k ? for rise/fall times of 11 ns. 7 riser input connected to vcc by a resistor that selects rise time of the uplink signal. typical value is r rise = 10 k ? for rise/fall times of 11 ns. 8, 14, 15 nc do not connect. leave these pins floating. used for internal testing. gnd tab 16 15 14 13 5 6 7 8 1 2 3 4 12 11 10 9 vcc ampr gnd gnd sdon nc sdop gnd eqco62r20.3 sdin nc sdip gnd vcc lfi riser nc downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 6 ? 2012-2016 microchip technology inc. 1.1.1 sdip/sdin sdip/sdin together form a differential input pair. it is the differential voltage between these pins that the eqco62r20 analyzes and adaptively equalizes for signal level and frequency response. the equalizer automatically detects and adapts to signals with different edge rates, different attenuation levels and different cable characteristics. both sdip and sdin inputs are terminated by 60 ? to vcc on-chip. for each input, an external 15 ? resistor is required in series. 1.1.2 sdop/sdon sdop/sdon together form a differential pair, outputting the reconstructed far-end transmit signal. sdop/sdon are terminated on-chip with 2x50 ? resistors. 1.1.3 lfi lfi is the uplink input signal that will be transmitted on the sdip/sdin pair. lfi must be a 1.2v lvttl signal. for 2.5v and 3.3v input swing, an external resistor is needed in series at the input of the chip. 1.1.4 ampr ampr is a vcc resistor that sets the transmit amplitude of the uplink output driver. the typical value for coaxpress is r amp = 1.2 k ? for 130 mv transmit amplitude. 1.1.5 riser riser is a vcc resistor that selects the rise/fall time of the uplink output driver. the typical value for coaxpress is r rise = 10 k ? for rise/fall time of 11 ns. if no r amp and r rise are placed, the lf driver is disabled. downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 7 eqco62r20.3/eqco31r20.3 1.2 circuit operation figure 1-3: eqco62r20.3 block diagram showing electrical connections 1.2.1 lf pre-driver the uplink pre-driver converts the incoming lvttl signal at the lfi pin to a signal with well-controlled amplitude and rise/fall times that will be transmitted onto the cable by the active splitter/combiner. 1.2.2 active signal splitter/ combiner the active splitter/combiner transmits the outgoing coax signal via an internal 60 ? output termination resistor. the total (60 ? + 15 ? ) output resistor, when balanced with the coax characteristic impedance, also forms part of a hybrid splitter circuit which subtracts the tx output from the signal on the sdi output to give yield the far-end tx signal. eqco62r20.3 rx output driver active signal splitter/combiner lf pre- driver sdip sdop lfi equalizer core sdin sdon downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 8 ? 2012-2016 microchip technology inc. figure 1-4: principle of equalizer operation 1.2.3 equalizer core the eqco62r20 has an embedded equalizer in the receive path with the following characteristics: auto-adaptive the equalizer controls a multiple-pole analog filter which compensates for attenuation of the cable, as illustrated in figure 1-4 . the filter frequency response needed to restore the signal is automatically determined by the device using a time-continuous feedback loop that measures the frequency components in the signal. upon the detection of a valid signal, the control loop converges within a few microseconds. variable gain the eqco62r20 equalizer has variable gain to compensate for low-frequency attenuation through the coax and variations in transmit amplitude. multi-speed the eqco62r20 works at data rates from 1.25 gbps to 6.25 gbps with 8b/10b coding. example equalizer performance measurements can be found in figure . 1.2.4 rx output driver the output driver converts the output of the equalizer core to a lvds-like signal and sends it onto a 100 ? differential transmission line. downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 9 eqco62r20.3/eqco31r20.3 2.0 application information figure 2-1 illustrates a typical schematic implementation. figure 2-1: eqco62r20.3 ty pical application circuit table 2-1: component recommendation for the eqco62r20.3 board layout element value size recommended component fb1, fb2 1 k ? @ 100 mhz ferrite bead 0603 fbmh1608hm102 from taiyo yuden (critical) l1 10 h 1812 1812ps_103 or ja4644-al from coilcraft (critical) r1, r2 15 ? 1% 0402 r3 75 ? 1% 0402 r4 0 ? (1.2v input swing) 3.9 k ? (2.5v input swing) 6.2 k ? (3.3v input swing) r amp 1.2 k ? 1% r rise 10 k ? 1% c1 100 nf, 50v, x7r 0603 c2, c3, c4, c5, c6 100 nf, x7r 0402 c7 10nf, 50v, x7r 0402 c8 1 f, 50v, x7r 0805 bnc1 75 ? right angle bnc connector bnc-ra c-sx-090 from cambridge connectors downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 10 ? 2012-2016 microchip technology inc. ferrite beads fb1 and fb2 (fbmh1608hm102 from taiyo yuden) and inductor l1 (1812ps_103 from coilcraft [10 h]) are recommended for coaxpress. for other applications, the inductor value can be larger, leading to a physical larger inductor. connector bnc1 (75 ? right angle bnc c-sx-090 from cambridge) is recommended for coaxpress. other inductors/ferrite beads/bnc connectors can possibly be used, however, they must be selected carefully for their rf-performance, since performance can decrease significantly. 2.1 guidelines for pcb layout when using the eqco62t/r20 chipset at its full purpose, i.e. including low-speed uplink and power supply transmission, it is important not to disturb the rf-performance of the high-speed downlink channel. implementing the circuit illustrated in figure 2-1 with a different pcb layout will in first instance not deliver full data sheet performance. the simplest way of meeting optimal performance, including jitter and return-loss requirements, is to precisely follow the component and layout recommendations. note that at multi-gigabit speeds, using "equivalent" components or small pcb layout changes (even moving a via) can have significant detrimental effects. the easiest way for achieving the requirements of the coaxpress 1.1 specification is to use the recommended circuits, components and layout illustrated in figure 2-1 . for easy implementation, microchip will provide the gerber file. please ask for it by email. 2.1.1 right angle bnc figure 2-2 below shows the four layers of the recommended footprint for the eqco62r20.3 chip and the off-chip components that are critical for the rf-performance of the system. figure 2-2: recommended pc b layout for eqco62r20.3 in this layout, the size of the pcb area needed for the chip is minimized. approximately two times the bnc footprint area is required for the full bidirectional system: including the necessary elements for the power transport. the differential output of the chip must be a 100 ? differential transmission line. to minimize the parasitic capacitance of the input pins, a cut-out of the ground note: email address: coaxpress@microchip.com downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 11 eqco62r20.3/eqco31r20.3 and power plane underneath the input pins is recommended. for best performance, no vias should be used in this high-speed signal path. a large cut-out underneath the right angle bnc connector, the ac coupling capacitors, ferrite beads and inductor is needed for minimal parasitics. this proposed layout is designed to be largely independent of the used pcb-layer stack. this will work as well for four, six or even higher numbers of layers. possible extra layers should have cut-outs as large as the full proposed footprint. figure 2-3: pcb layout of multil ane coaxpress 0v1 demo board pair camera side 5x6.25gb/s + 5x21mb/s host side cd_1 cd_2 cd_3 cd_4 eq_5 cd_5 eq_4 eq_3 eq_2 eq_1 downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 12 ? 2012-2016 microchip technology inc. 2.1.2 multilane coaxpress 4+1 layout with din1.0/2.3 connectors figure 2-3 shows an example of a multilane coaxpress 4+1 setup. the recommended din1.0/2.3 connector is the npf 4076 from cambridge connectors. the cable example shows the pitches in millimeters. figure 2-4 shows the four layers of the recommended footprints and off-chip components that are critical for rf-performance of the cable drivers cd_1 to cd_4 at the camera side, which have power over coaxpress (pocxp). figure 2-5 shows the variant without pocxp used for cd_5 at the host side. the exact dimensions in millimeters are given in section 4.1 package marking information . it is recommended to copy these dimensions, especially the connection between the din1.0/2.3 connector and the chip, as this is a complex entity with coupled currents and compensated parasitic capacitances. despite the critical layout, this proposed layout is designed to be largely independent of the used pcb- layer stack, as the critical parts are mainly the top-layer only. this will work as well for four, six or even higher numbers of layers. possible extra layers should have cut-outs as large as the full proposed footprint. in these layouts, the size of the pcb area needed for the chip is minimized. this allows multiple lanes close together. only two of four connector gnd pins are connected to the gnd plane to reduce the capacitance. the differential cd inputs must be a 100 ? differential transmission line. a cut-out of the ground and power plane underneath the input pins is recommended to minimize the parasitic capacitance. for best performance, no vias should be used in this high-speed signal path. the components express 4+1 connector in figure 2-3 is only shown as an example. other connector configurations are available with din1.0/2.3 connectors such as 6+1, 2+1, 1+1, dual- or single-lane configurations. downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 13 eqco62r20.3/eqco31r20.3 figure 2-4: recommended pcb layout for eqco62r20.3 with din1.0/2.3 connector with pocxp top ground power bottom v3 v4 v5 v6 v7 a b c d e l m n o p q r t u f g h i j k s v1 v2 v8 downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 14 ? 2012-2016 microchip technology inc. figure 2-5: recommended pcb layout for eqco62r20.3 with din1.0/2.3 connector without pocxp top ground power bottom v2 v3 v1 v4 v6 v7 d e f g k l m o p n q r s h i j t v5 b c a downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 15 eqco62r20.3/eqco31r20.3 2.2 guidelines for power transmit unit at the power-in connection, a voltage supply is expected for powering a device (e.g. a camera) at the other end of the cable. this voltage supply should have low ripple. high- frequency ripple will be rejected by c8/l1/fb1/fb2 filtering in the reference circuit. however, mid-frequency ripple is to be avoided by the power supply itself. in a typical application, one could want to step-up from a 12v supply (e.g. in a pc) to a 24v power supply for coaxpress. it is in this case preferred to use a dc-to- dc converter that has a high switching frequency (e.g. 2 mhz) above one that has lower switching frequency (200 khz). the latter typically induces larger voltage spikes at the power-in connection. these will be only partially filtered out by said filter; the remainder will become crosstalk for the uplink channel. when too much crosstalk remains on the uplink channel, additional power-supply filtering is required. this may be achieved by placing an extra filter network (not shown) in series with the power-in node. 2.3 power over coaxpress the eqco62r20.3 is compatible with the power over coaxpress system (pocxp) using the circuit from figure 2-2 . hence, power can be switched on and off by the host (e.g. frame grabber) through the 10 h inductor specified by the cxp standard. this switching is supported through a relay and through an electronic switch. powering through a wide-band bias-t is also supported. the eqco62r20.3 is also protected against the following events: hot plugging by frame grabber: in case the frame grabber has already applied its 24v on the coax when connecting the cable, no damage will occur to the eqco62r20.3 when connecting the powered coax cable. fast turn-on and turn-off of power supply by frame grabber. downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 16 ? 2012-2016 microchip technology inc. 3.0 electrical characteristics 3.1 absolute maximum ratings stresses beyond those listed under this section may cause permanent damage to the device. these are stress ratings only and are not tested. functional operation of the device at these or any other conditions beyond those indicated in the operational sections is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3-1: absolute maximum ratings parameter conditions min. typ. max. units storage temperature -65 +150 c ambient temperature power applied -55 +125 c operating temperature normal operation (vcc = 1.2v 5%) -40 +85 c supply voltage to ground -0.5 +1.4 v dc input voltage -0.5 +1.6 v dc voltage to outputs -0.5 +1.6 v current into outputs outputs low 90 ma table 3-2: electrical characteristics (ove r the operating vcc and -40 to +85c range) parameter description min. typ. max. unit power supply vcc supply voltage 1.15 1.2 1.25 v i s supply current, both transmitting and receiving 60 ma i sr supply current when only receiving 50 ma lfi input (lvttl-like) ? v ih input high voltage 1.2 1.6 v v il input low voltage -0.5 gnd v r input resistance to gnd 3.6 k ? sdip connection to coax z coax coax cable characteristic impedance 75 ? r sdi p input impedance between sdop and vcc/gnd 75 ? v lf coax return loss as seen on sdop pin frequency range = 5 mhz-1 ghz - 1 5d b t rise_lf coax return loss as seen on sdop pin frequency range = 1 ghz-1.5 ghz - 1 0d b rl loss coax return-loss as seen on sdip pin frequency range = 5 mhz-1 ghz - 1 5d b rl loss coax return-loss as seen on sdip pin frequency range = 1 ghz-1.5 ghz - 1 0d b rl loss coax return-loss as seen on sdip pin frequency range = 1.5 ghz-3.2 ghz - 7d b ? v tx transmit amplitude for downlink signal 500 600 700 mv downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 17 eqco62r20.3/eqco31r20.3 1: jitter in equalizer output measured as 8b/10b coded signal over full transmit amplitude, vcc and temperature range, including uplink and power supply transmission. sdop/sdon outputs ? v o output amplitude v sdop,n (into 2x50 ? ) 2x600 mv r output termination between sdop/sdon and gnd/vcc 2x50 ? t rise_o rise/fall time 20% to 80% of v sdop,n 4 0p s table 3-2: electrical characteristics (ove r the operating vcc and -40 to +85c range) (continued) table 3-3: jitter numbers parameter conditions min. typ. max. units additive jitter on lf output 8b/10b coded signal at 21 mbps over full vcc and temperature range 1n s dcd in lf output 8b/10b coded signal at 21 mbps over full vcc and temperature range 3n s jitter in equalizer output at 1.25 gbps from 0 to 135m belden 1694a = -22 db attenuation at 0.625 ghz ( 1 ) 0 . 3u i jitter in equalizer output at 1.25 gbps from 0 to 115m belden 1694a = -27.2 db attenuation at 1.25 ghz ( 1 ) 0 . 3u i jitter in equalizer output at 1.25 gbps from 0 to 105m belden 1694a = -28.1 db attenuation at 1.5625 ghz ( 1 ) 0 . 3u i jitter in equalizer output at 1.25 gbps from 0 to 65m belden 1694a = -22.6 db attenuation at 2.5 ghz ( 1 ) 0 . 3u i jitter in equalizer output at 1.25 gbps from 0 to 45m belden 1694a = -17.8 db attenuation at 3.125 ghz ( 1 ) 0 . 3 5u i downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 18 ? 2012-2016 microchip technology inc. 4.0 packaging information 4.1 package marking information 16-lead plastic quad flat, no lead package 4x4x0.9 mm body [qfn] 16-lead qfn (4x4x0.9 mm) example pin 1 pin 1 eqco 62r20.3 yywwnnn yywwnnn legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 19 eqco62r20.3/eqco31r20.3 b a 0.20 c 0.20 c (datum b) (datum a) c seating plane 1 2 n 2x top view side view bottom view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: note 1 1 2 n 0.10 c a b 0.10 c a b 0.10 c 0.08 c microchip technology drawing c04-259b sheet 1 of 2 16-lead plastic quad flat, no lead package (8e) - 4x4x0.9 mm bod [qfn] d e 2x 16x (a3) a d2 e2 16x l 16x b e e 2 (16x k) a1 0.10 c a b 0.05 c downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 20 ? 2012-2016 microchip technology inc. microchip technology drawing c04-259b sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of pins overall height terminal width overall width overall length terminal length exposed pad width exposed pad length terminal thickness pitch standoff units dimension limits a1 a b d e2 d2 a3 e l e n 0.65 bsc 0.20 ref 1.951.95 0.45 0.25 0.80 0.00 0.30 4.00 bsc 0.55 2.05 2.05 0.870.02 4.00 bsc millimeters min nom 16 2.152.15 0.65 0.35 0.950.05 max k 0.425 ref ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1.2. 3. noes: pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m terminal-to-exposed-pad 16-lead plastic quad flat, no lead package (8e) - 4x4x0.9 mm bod [qfn] downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 21 eqco62r20.3/eqco31r20.3 recommended land pattern for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch y2 x2 2.15 2.15 millimeters 0.65 bsc min e max 3.625 contact pad length (x16) contact pad width (x16) y1 x1 0.725 0.30 bsc: basic dimension. theoretically exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m microchip technology drawing c04-2259a nom 16-lead plastic quad flat, no lead package (8e) - 4x4x0.9 mm bod [qfn] silk screen 12 16 c1 contact pad spacing 3.625 contact pad to center pad (x16) g1 0.20 c1 c2 y2 x2 y1 g1 x1 e downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 22 ? 2012-2016 microchip technology inc. appendix a: revision history revision b (march 2016) updated section 4.0, packaging information . removed electrostatic discharge ratings from table 3-1 . minor typographical changes. revision a (august 2014) this is the initial release of the document in the microchip format. this replaces eqcologic docu- ment version 1v2. table a-1: revision history version date comments 1v2 1/27/14 added references 1v1 4/10/12 added multilane coaxpress 4+1 layout with din1.0/2.3 connectors 1v0 2/9/12 initial release of this document downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 23 eqco62r20.3/eqco31r20.3 appendix b: typical line equalizer characteristics all measurements at vcc = 1.2v, temp = +25oc, data pattern = 8b/10b test pattern, 600 mv transmit amplitude usin g belden 1694a coaxial cable, and include uplink and power supply transmission over the cable with differential measurement into 2x50 ? . figure b-1: 1.25 gbps, 135m belden 1694a figure b-2: 3.125 gbps, 105m belden 1694a figure b-3: 6.25 gbps, 45m belden 1694a (eqco62r20 only) figure b-4: 2.5 gbps, 115m belden 1694a figure b-5: 5 gbps, 65m belden 1694a (eqco62r20 only) downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 24 ? 2012-2016 microchip technology inc. appendix c: typical uplink characteristics all measurements at vcc = 1.2v, temp = +25oc, data pattern = 8b/10b test pattern at 21 mbps, typi cal r amp and r rise , measured into 75 ? . figure c-1: signal transmitted by low- speed driver showing basline wander due to external 10 h inductor and ferrite beads ( 1 ) 1: inductor and ferrite beads at the camera side of the link will double the baseline wandering. this is resolved by the lf-receiver in the eqco62t20 chip. figure c-2: output eye of lf driver with and without external 10 h inductor with external 10 h inductor without external 10 h inductor downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 25 eqco62r20.3/eqco31r20.3 appendix d: typical return-loss figure d-1 shows the return-loss at the bnc connector of the eqco62r20.3 evaluation board as shown in section 2.0 application information with supply current of 0 ma and 703 ma (maximum supply current for coaxpress) through the inductor (l1) and the ferrite beads (fb1 & fb2) and compares it with the coaxpress (full-speed) return-loss specification. figure d-1: return-loss of the eqco 62r20.3 bnc evaluation board with and without supply current downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 26 ? 2012-2016 microchip technology inc. appendix e: footprints used for the multilane coaxpress layout figure e-1: 0402, 0603 and via wi th thermal isolation footprints figure e-2: din1.0/2.3 and l1 inductor 1812 footprints table e-1: component positions of figure 2-4 component footprint x y angle npf 4076 din1.0/2.3 0 0 bottom eqco62r20.3 qfn -0.075 -8 c1 (50v) 0603 0.075 -2.55 90 c2 0402 2.4 -4.9 90 r1 (16 ? ) 0402 0.25 -4.575 90 r2 (91 ? ) 0402 -1.2 -5 fb1 0603 -2.05 0.6 fb2 0603 -2.05 -0.6 r6 0402 4.075 0.35 c7 (50v) 0402 4.475 1.850 90 c9 0402 1.675 -11.025 c10 0402 2.05 -4.9 0.52 0.52 0.40 0.90 0.75 0.60 1.20 ? 0.71 copper ? 0.35 drill 0.30 2.54 2.54 ? 1.50 copper ? 0.80 drill ? 2.60 copper ? 1.60 drill 3.00 1.60 2.28 downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 27 eqco62r20.3/eqco31r20.3 table e-2: via positions of figure 2-4 table e-3: ground and vcc plane position of figure 2-4 l1 1812 4.5 -7.6 90 bottom c8 (50v) 0603 -0.725 -8.425 bottom c5 0402 -0.125 -7.175 bottom via thermal x y connected to 1 4.1 -4.1 top-bottom 2 4.825 -4.1 top-bottom 3 not isolated -1.725 -5.975 top-gnd-bottom 4 not isolated 1.7 -6.425 top-power-bottom 5 -2.9 -7.025 top-bottom 6 isolated 1.65 -9.9 top-gnd-bottom 7 isolated 1.575 -9.7 top-gnd 8 not isolated 2.375 -10.175 top-power gnd plane coordinates x y vcc plane coordinates x y a -2.475 -9.1 n -2.475 -9.125 b -2.475 -3.1 o -2.475 -6.875 c -1.25 -3.1 p 0.75 -6.875 d -1.25 -6.125 q 0.75 -6.05 e -0.475 -6.9 r 2.475 -6.05 f 0.85 -6.9 s 2.475 -9.125 g0 . 8 5 - 5 . 9 7 5 h1 . 0 5 - 5 . 7 7 5 i1 . 0 5 - 3 . 1 j -2.475 -3.1 k 2.475 -9.1 l -0.9 -9.075 t -0.9 -9.075 m 0.75 -10.725 u 0.75 -10.725 figure e-3: track dimensions of figure 2-4 track width 1 0.3 qfn.1 to tab (gnd) 2 0.4 qfn.1 to c10 (gnd) 3 0.3 qfn.2 (sdip) 4 0.2 qfn.3 (sdin) 5 0.3 qfn.4 (gnd) 60 . 2 q f n . 5 ( l f i n ) 70 . 2 q f n . 6 ( a m p r ) 8 0.2 qfn.7 (riser) 9 0.3 qfn.9 (gnd) 10 100 ? diff. ( 1 ) qfn.10-11 (sdip-sdin) 11 0.3 qfn.12 to v8/tab (gnd) note 1: width and spaces between lines needs to be calculated based on pcb layer stack. impedance should be 100 ? differential. component footprint x y angle downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 28 ? 2012-2016 microchip technology inc. table e-4: component positions of figure 2-5 table e-5: via positions of figure 2-5 12 0.4 qfn.12 to c9 (gnd) 13 0.4 qfn.13 (vcc) 14 0.5 c9 to v9 (vcc) 15 0.5 qfn.16 16 0.4 c2 to din1.0/2.3 17 0.7 c10 to din1.0/2.3 18 0.3 r1 19 0.4 c1 to din1.0/2.3 20 0.4/0.7 fb 21 0.2 c7 22 0.5 bottom tracks component footprint x y angle npf 4076 din1.0/2.3 0 0 bottom eqco62r20.3 qfn -0.075 -7.725 c1 (50v) 0603 0.5 -2 90 c2 0402 -0.75 -2.4 90 r1 (16 ? ) 0402 0.5 -4.05 90 r2 (91 ? ) 0402 -0.8 -4.05 90 c5 0402 -2.4 -4.925 c9 0402 2.925 -9.1 90 c10 0402 2.225 -4.925 bottom via thermal x y connected to 1 isolated -2.8 -5.625 top-power 2 not isolated -1.675 -5.65 top-gnd 3 not isolated 1.6 -5.65 top-gnd 4 not isolated 2.325 -6.225 top-power 5 isolated 2.675 -8 top-power 6 isolated -1.65 -9.5 top-gnd 7 isolated 1.55 -9.5 top-gnd figure e-3: track dimensions of figure 2-4 track width note 1: width and spaces between lines needs to be calculated based on pcb layer stack. impedance should be 100 ? differential. downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 29 eqco62r20.3/eqco31r20.3 table e-6: ground plane position of figure 2-5 note 1: width and spaces between lines need to be calculated based on pcb layer stack. impedance should be 100 ? differential. figure e-5: used layer stack gnd plane coordinates x y vcc plane coordinates x y a -1.725 3.75 m -2.3 -3.475 b -1.725 -3 n -2.3 -6.65 c -2.25 -3 o 1.75 -6.65 d -2.25 -5.2 p 1.75 -5.575 e -0.425 -7 q 2.85 -5.575 f 0.225 -7 r 2.85 -10.075 g1 . 6 5 - 5 . 5 7 5 h1 . 6 5 - 3 i2 . 8 5 - 3 j 2.85 -10.075 k -0.9 -8.8 s -0.9 -8.8 l 0.75 -10.45 t 0.75 -10.45 figure e-4: track widths of figure 2-5 track width 1 0.3 qfn.1; qfn.4 (gnd) 2 0.3 qfn.2 (sdip) 3 0.3 qfn.3 (sdin) 40 . 2 q f n . 5 ( l f i n ) 50 . 2 q f n . 6 ( a m p r ) 6 0.2 qfn.7 (riser) 7 0.3 qfn.9; qfn.12 (gnd) 8 100 ? diff. ( 1 ) qfn.10-11 (sdip-sdin) 9 0.5 qfn.13; qfn.16 (vcc) 10 0.5 c9; c10; c5 11 0.4 c1; c2 downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 30 ? 2012-2016 microchip technology inc. the microchip web site microchip provides online support via our web site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 31 eqco62r20.3/eqco31r20.3 product identification system to order parts, including industrial, or obtain information, for e.g., on pricing or delivery, re fer to the factory or the list ed sales office . part no. xxx rm radio firmware device device: eqco62r20.3 temperature range: i = -40 ? cto+85 ? c (industrial temperature) package: tray = tray (blank) = tube examples: a) eqco62r20.3 = industrial temperature, 16-lead qfn tube packaging b) eqco62r20.3-tray = industrial temperature, 16-lead qfn tray packaging i temp. range module revision number f f downloaded from: http:///
eqco62r20.3/eqco31r20.3 ds60001302b-page 32 ? 2012-2016 microchip technology inc. notes: downloaded from: http:///
? 2012-2016 microchip technology inc. ds60001302b-page 33 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012-2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0372-2 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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